US 12,034,457 B2
Memory, memory module, memory system, and operation method of memory system
Seok Woo Choi, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 15, 2022, as Appl. No. 17/986,968.
Claims priority of application No. 10-2022-0087315 (KR), filed on Jul. 15, 2022.
Prior Publication US 2024/0022263 A1, Jan. 18, 2024
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/1191 (2013.01) [H03M 13/611 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A memory system comprising:
an error correction code generation circuit configured to generate a first error correction code having a first parity and a second parity by using write data and a first H matrix having a first parity matrix for generating the first parity and a second parity matrix for generating the second parity in a first error correction mode, and to generate a second error correction code having the first parity by using the write data and a second H matrix having the first parity matrix in a second error correction mode; and
a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.