US 12,034,451 B2
Successive approximation register analog to digital converter device and signal conversion method
Jun Yang, Suzhou (CN); Shih-Hsiung Huang, Hsinchu (TW); and Yen-Ting Wu, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Jul. 22, 2022, as Appl. No. 17/870,958.
Claims priority of application No. 202111191315.5 (CN), filed on Oct. 13, 2021.
Prior Publication US 2023/0116785 A1, Apr. 13, 2023
Int. Cl. H03M 1/34 (2006.01); H03M 1/12 (2006.01); H03M 1/46 (2006.01)
CPC H03M 1/462 (2013.01) [H03M 1/1245 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A successive approximation register analog to digital converter device, comprising:
a first digital to analog converter circuit;
a second digital to analog converter circuit configured to cooperate with the first digital to analog converter circuit to sample an input signal;
a comparator circuit configured to generate a plurality of first comparison results according to an output of the first digital to analog converter circuit and an output of the second digital to analog converter circuit;
a controller circuit configured to generate a plurality of first bits and a plurality of second bits according to the plurality of first comparison results and store the plurality of first bits and a plurality of second bits, wherein the plurality of second bits are for switching the second digital to analog converter circuit; and
a dynamic element matching circuit configured to encode the plurality of first bits to generate a plurality of third bits, in order to fresh the first digital to analog converter circuit,
wherein after the first digital to analog converter circuit is refreshed, the controller circuit is further configured to reset partial bits in the plurality of second bits, the comparator circuit is further configured to generate a plurality of second comparison results according to the output of the first digital to analog converter circuit and the output of the second digital to analog circuit after the partial bits are reset, and the controller circuit is further configured to generate a plurality of fourth bits according to the plurality of second comparison results and generate a digital output according to the plurality of first bits, the plurality of second bits, and the plurality of fourth bits.