US 12,034,446 B2
Fused memory and arithmetic circuit
Daniel Pugh, Los Gatos, CA (US); Raymond Nijssen, San Jose, CA (US); and Michael Philip Fitton, Menlo Park, CA (US)
Assigned to Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed by Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed on Jul. 28, 2020, as Appl. No. 16/940,878.
Application 16/940,878 is a continuation of application No. 16/417,152, filed on May 20, 2019, granted, now 10,790,830.
Prior Publication US 2020/0373925 A1, Nov. 26, 2020
Int. Cl. H03K 19/1776 (2020.01); H03K 19/17736 (2020.01)
CPC H03K 19/1776 (2013.01) [H03K 19/17744 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first memory circuit operable to:
receive an address input from a connection fabric of a field programmable gate array (FPGA), an intra-tile connection, or a cascade connection; and
provide a first data output based on the address input;
a second memory circuit operable to:
receive the address input; and
provide a second data output based on the address input; and
a multiplexer operable to:
receive a configuration input; and
based on the configuration input, provide either the first data output or the second data output.