US 12,034,443 B2
Memory device
Junya Matsuno, Yokohama Kanagawa (JP); Kensuke Yamamoto, Yokohama Kanagawa (JP); Ryo Fukuda, Yokohama Kanagawa (JP); Masaru Koyanagi, Tokyo (JP); Kenro Kubota, Fujisawa Kanagawa (JP); and Masato Dome, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 22, 2023, as Appl. No. 18/125,081.
Application 17/588,702 is a division of application No. 17/002,816, filed on Aug. 26, 2020, granted, now 11,277,134, issued on Mar. 15, 2022.
Application 18/125,081 is a continuation of application No. 17/588,702, filed on Jan. 31, 2022, granted, now 11,637,555.
Claims priority of application No. 2020-007863 (JP), filed on Jan. 21, 2020.
Prior Publication US 2023/0223938 A1, Jul. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 7/06 (2006.01); G11C 11/419 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 19/018521 (2013.01) [G11C 7/1048 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); H03K 19/018571 (2013.01); G11C 7/065 (2013.01); G11C 7/1087 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a memory cell array configured to store data; and
a signal propagation circuit configured to propagate a signal between the memory cell array and a host, the signal propagation circuit including:
a first inverted signal output circuit,
a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and
a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.