US 12,034,440 B2
Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed links
Rajesh Kumar, Santa Clara, CA (US); Edoardo Prete, Boxborough, MA (US); Gerald R. Talbot, Boxborough, MA (US); Ethan Crain, Boxborough, MA (US); Tracy J. Feist, Fort Collins, CO (US); and Jeffrey Cooper, Fort Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 30, 2021, as Appl. No. 17/566,199.
Claims priority of provisional application 63/275,852, filed on Nov. 4, 2021.
Prior Publication US 2023/0134926 A1, May 4, 2023
Int. Cl. H03K 19/01 (2006.01); H03K 19/0175 (2006.01); H03F 3/45 (2006.01)
CPC H03K 19/017509 (2013.01) [H03F 3/45475 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first interface configured to receive a first input signal from a transmission line;
a circuit coupled to the first interface and configured to generate an output signal as a baseline wander corrected version of the first input signal, wherein the circuit comprises:
a resistor-capacitor parallel arrangement; and
one or more current sources connected to a first end of the resistor-capacitor parallel arrangement; and
one or more current sources connected to a second end of the resistor-capacitor parallel arrangement, wherein each current source on each of the first end and the second end is configured to receive a control signal based on a sensed common mode voltage of the first input signal and a second input signal different from the first input signal; and
a second interface configured to receive the output signal from the circuit.