US 12,034,072 B2
Semiconductor devices having unit cell transistors with smoothed turn-on behavior and improved linearity
Yueying Liu, Morrisville, NC (US); Saptharishi Sriram, Cary, NC (US); Scott Sheppard, Chapel Hill, NC (US); and Jennifer Gao, Burlington, NC (US)
Assigned to MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Mar. 3, 2021, as Appl. No. 17/190,559.
Application 17/190,559 is a division of application No. 16/194,760, filed on Nov. 19, 2018, granted, now 10,978,583.
Application 16/194,760 is a continuation in part of application No. 15/628,932, filed on Jun. 21, 2017, granted, now 10,615,273, issued on Dec. 27, 2018.
Prior Publication US 2021/0193825 A1, Jun. 24, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 27/085 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H03F 3/193 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01); H03F 3/42 (2006.01); H01L 29/20 (2006.01)
CPC H01L 29/7787 (2013.01) [H01L 27/085 (2013.01); H01L 29/0696 (2013.01); H01L 29/42316 (2013.01); H01L 29/7786 (2013.01); H03F 3/193 (2013.01); H03F 3/195 (2013.01); H03F 3/21 (2013.01); H03F 3/211 (2013.01); H03F 3/423 (2013.01); H01L 29/2003 (2013.01); H03F 2200/366 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of unit cell transistors on a semiconductor structure, the semiconductor structure including a gallium nitride based barrier layer, the unit cell transistors electrically connected in parallel, and each of the unit cell transistors including a respective gate finger; and
a voltage divider circuit that includes a first output that is coupled to the respective gate fingers of a first subset of the unit cell transistors and a second output that is coupled to the respective gate fingers of a second subset of the unit cell transistors,
wherein the first and second outputs are configured to apply first and second voltages to the respective gate fingers of the first and second subsets of the unit cell transistors, respectively,
wherein the first and second voltages differ by at least 0.1 volts.
 
11. A semiconductor device, comprising:
a wafer having a gallium nitride based layer;
a plurality of unit cell transistors on/in the wafer, the unit cell transistors electrically connected in parallel and each of the unit cell transistors including a respective gate finger; and
a voltage divider circuit that is at least partially on the wafer, the voltage divider circuit including a first output that is coupled to gate fingers of a first subset of the unit cell transistors, a second output that is coupled to gate fingers of a second subset of the unit cell transistors, and a first resistor that is coupled between the first output and the second output.