US 12,034,047 B2
Semiconductor device including oxide semiconductor layer
Woo Bin Song, Hwaseong-si (KR); Sang Woo Lee, Seoul (KR); and Min Hee Cho, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 18, 2022, as Appl. No. 18/056,954.
Application 18/056,954 is a continuation of application No. 16/796,273, filed on Feb. 20, 2020, granted, now 11,532,707.
Claims priority of application No. 10-2019-0067692 (KR), filed on Jun. 10, 2019.
Prior Publication US 2023/0081793 A1, Mar. 16, 2023
Int. Cl. H01L 29/51 (2006.01); H01L 29/08 (2006.01); H01L 29/24 (2006.01); H01L 29/267 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0847 (2013.01) [H01L 29/24 (2013.01); H01L 29/267 (2013.01); H01L 29/41733 (2013.01); H01L 29/41775 (2013.01); H01L 29/45 (2013.01); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/7869 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a metal oxide layer disposed on the substrate;
a gate structure disposed on the metal oxide layer, the gate structure including an insulating material layer and a gate electrode disposed on the insulating material layer, the insulating material layer including a ferroelectric material layer;
an interlayer insulating layer covering the gate structure and disposed on the metal oxide layer; and
a contact disposed in the interlayer insulating layer and connected to the metal oxide layer,
wherein the gate structure includes gate spacers defining a gate trench,
wherein the ferroelectric material layer extends along sidewalls and a bottom surface of the gate trench,
wherein a top surface of the ferroelectric material layer is lower than a top surface of the gate spacers, and
the contact is in direct contact with the gate spacers.