US 12,034,043 B2
Integrated circuit device and method of manufacturing the same
Jinbum Kim, Seoul (KR); Gyeom Kim, Hwaseong-si (KR); Hyojin Kim, Hwaseong-si (KR); Haejun Yu, Osan-si (KR); Seunghun Lee, Hwaseong-si (KR); and Kyungin Choi, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 20, 2021, as Appl. No. 17/479,424.
Claims priority of application No. 10-2021-0031467 (KR), filed on Mar. 10, 2021.
Prior Publication US 2022/0293730 A1, Sep. 15, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0665 (2013.01) [H01L 29/0653 (2013.01); H01L 29/6656 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a fin-type active region extending in a first horizontal direction on a substrate;
a channel region on the fin-type active region;
a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction;
an insulating spacer covering a sidewall of the gate line;
a source/drain region connected to the channel region on the fin-type active region and comprising a first portion facing the sidewall of the gate line with the insulating spacer therebetween;
an air gap between the insulating spacer and the first portion of the source/drain region;
an insulating liner comprising a portion in contact with the source/drain region and a portion defining a size of the air gap; and
a device isolation layer between the substrate and the gate line and covering a sidewall of the fin-type active region,
wherein the air gap comprises a portion between a top surface of the device isolation layer and the source/drain region.