| CPC H01L 29/0649 (2013.01) [H01L 29/41791 (2013.01); H01L 29/42364 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
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1. A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure crossing active regions on a substrate;
forming a gate spacer contacting a side surface of the gate structure;
forming a source/drain region on the side surface of the gate structure;
recessing the gate structure;
forming a lower source/drain contact plug connected to the source/drain region;
forming a gate isolation layer on the gate spacer;
forming a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer; and
forming an upper source/drain contact plug on the lower source/drain contact plug, such that the upper source/drain contact plug penetrates the capping layer and contacts the lower source/drain contact plug.
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