US 12,034,034 B2
Method of manufacturing capacitor array
Zhi-Xuan Shen, Taipei (TW); and Yu-Shan Wu, Tainan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jan. 26, 2022, as Appl. No. 17/584,636.
Prior Publication US 2023/0238424 A1, Jul. 27, 2023
Int. Cl. H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/40 (2013.01) [H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32135 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for manufacturing a capacitor array, comprising:
depositing a sacrificial layer on a bottom electrode;
depositing an insulative layer on the sacrificial layer;
forming a polysilicon hardmask on the insulative layer;
etching the insulative layer and the sacrificial layer exposed through a plurality of openings in the polysilicon hardmask to form channels;
depositing a metal film on the polysilicon hardmask and in the channels;
depositing a passivation film on the metal film;
performing a first removal process to remove portions of the passivation film and the metal film over the polysilicon hardmask;
performing a second removal process to remove portions of the polysilicon hardmask exposed through the passivation film and the metal film;
performing a third removal process to remove the polysilicon hardmask and portions of the passivation film and the metal film surrounding the polysilicon hardmask;
removing the passivation film and the metal film from the insulative layer and the sacrificial layer;
depositing a conductive material in the channels and in contact with the insulative layer and the sacrificial layer;
removing the sacrificial layer; and
forming a top electrode on the insulative layer.