| CPC H01L 27/11807 (2013.01) [H01L 23/481 (2013.01); H01L 27/0207 (2013.01); H01L 2027/11829 (2013.01); H01L 2027/11864 (2013.01); H01L 2027/11881 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a first standard cell and a second standard cell, the first standard cell and the second standard cell being disposed on a substrate, each of the first and second standard cells comprising an active region, a plurality of fin patterns disposed on the active region and extending in a first direction, a plurality of gate structures intersecting the plurality of fin patterns and extending in a second direction perpendicular to the first direction, a plurality of source/drain regions disposed on the plurality of fin patterns on both sides of each of the plurality of gate structures, and a contact structure connected to at least one of the plurality of source/drain regions and extending in a vertical direction, wherein the first and second standard cell are arranged in the second direction and shares a boundary with each other;
a power line disposed on a lower surface of the substrate and overlapping the boundary between the first standard cell and the second standard cell, the power line extending in the first direction;
a through conductive structure extending from the lower surface of the substrate toward an upper surface of the substrate, and connected to the power line; and
a buried conductive structure disposed on the substrate, and connected to the through conductive structure,
wherein the plurality of fin patterns of the first standard cell comprises an external fin pattern overlapping the power line in the vertical direction,
wherein the buried conductive structure is electrically connected to the contact structure and supplies power to the first standard cell and the second standard cell.
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