US 12,034,004 B2
Method (and related apparatus) for forming a semiconductor device with reduced spacing between nanostructure field-effect transistors
Zhi-Chang Lin, Zhubei (TW); Huan-Chieh Su, Tianzhong Township (TW); and Kuo-Cheng Chiang, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 2, 2023, as Appl. No. 18/328,117.
Application 17/729,390 is a division of application No. 16/929,592, filed on Jul. 15, 2020, granted, now 11,322,493, issued on May 3, 2022.
Application 18/328,117 is a continuation of application No. 17/729,390, filed on Apr. 26, 2022, granted, now 11,705,452.
Claims priority of provisional application 62/927,881, filed on Oct. 30, 2019.
Prior Publication US 2023/0317724 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/42392 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor fin projecting from a semiconductor substrate;
a plurality of semiconductor nanostructures that are disposed directly over the semiconductor fin and vertically stacked;
a gate electrode structure disposed over the semiconductor fin and around the semiconductor nanostructures; and
a dielectric fin disposed over the semiconductor substrate, wherein both the gate electrode structure and the semiconductor nanostructures are disposed on a first side of the dielectric fin, and wherein an upper surface of the dielectric fin is disposed below an upper surface of the gate electrode structure.