US 12,034,000 B2
Double IO pad cell including electrostatic discharge protection scheme with reduced latch-up risk
Michael A. Stockinger, Austin, TX (US); and Mohamed Suleman Moosa, Austin, TX (US)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Mar. 23, 2022, as Appl. No. 17/702,588.
Prior Publication US 2023/0307440 A1, Sep. 28, 2023
Int. Cl. H01L 27/02 (2006.01); H02H 9/04 (2006.01)
CPC H01L 27/0292 (2013.01) [H01L 27/0255 (2013.01); H01L 27/0296 (2013.01); H02H 9/046 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A double input-output (IO) pad cell formed on an integrated circuit (IC), the double IO pad cell comprising:
a busing frame having a specified length and specified height formed on a busing metal layer, wherein the busing frame comprises a first IO pad for a first IO signal, a second IO pad for a second IO signal, a supply voltage rail, and a ground voltage rail; and
a component frame having the specified length and the specified height integrated on a component layer aligned with the busing frame, the component frame comprising:
first primary electrostatic discharge (ESD) circuitry comprising a first diode coupled between the first IO pad and the supply voltage rail and a second diode coupled between the first IO pad and the ground voltage rail; and
second primary ESD circuitry comprising a third diode coupled between the second IO pad and the supply voltage rail and a fourth diode coupled between the second IO pad and the ground voltage rail;
wherein the second and fourth diodes are integrated adjacent each other sandwiched between the first and third diodes, wherein the first and second diodes are aligned with the first IO pad, and wherein the third and fourth diodes are aligned with the second IO pad.