US 12,033,968 B2
Package structure including stacked pillar portions
Jung-Hua Chang, Hsinchu (TW); Szu-Wei Lu, Hsinchu (TW); and Ying-Ching Shih, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 3, 2023, as Appl. No. 18/311,864.
Application 18/311,864 is a continuation of application No. 17/458,551, filed on Aug. 27, 2021, granted, now 11,682,645.
Application 17/458,551 is a continuation of application No. 16/572,611, filed on Sep. 17, 2019, granted, now 11,139,260, issued on Oct. 5, 2021.
Prior Publication US 2023/0275055 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/13 (2013.01) [H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/3185 (2013.01); H01L 23/49816 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 2224/11464 (2013.01); H01L 2224/13026 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16013 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a substrate;
a semiconductor die disposed over the substrate;
a first conductive bump disposed on and electrically connected to the semiconductor die, wherein a first width of a first end of the first conductive bump is greater than a second width of a second end of the first conductive bump, and the first end is opposite to the second end; and
a memory device disposed on and electrically connected to the substrate, wherein a first distance between the semiconductor die and the substrate is greater than a second distance between the memory device and the substrate, wherein the substrate comprises second conductive bumps, a third width of the second conductive bumps is greater than the second width of the second end, and the third width of the second conductive bumps is substantially equal to the first width of the first end.