US 12,033,948 B2
Semiconductor package
Young Lyong Kim, Anyang-si (KR); Hyunsoo Chung, Hwaseong-si (KR); and Inhyo Hwang, Asan-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 1, 2021, as Appl. No. 17/539,963.
Claims priority of application No. 10-2021-0083201 (KR), filed on Jun. 25, 2021.
Prior Publication US 2022/0415809 A1, Dec. 29, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5385 (2013.01) [H01L 23/3114 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate, wherein at least one first vent hole is centrally formed in the package substrate;
a first semiconductor chip mounted on the package substrate;
an interposer including supporters on a bottom surface of the interposer and at least one second vent hole centrally formed in the interposer, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals;
a second semiconductor chip mounted on the interposer; and
a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip, wherein the molding layer fills the at least one first vent hole, the at least one second vent hole, a space between the first semiconductor chip and the interposer, and a space between the second semiconductor chip and the interposer.