US 12,033,930 B2
Selectively roughened copper architectures for low insertion loss conductive features
Jieying Kong, Chandler, AZ (US); Yiyang Zhou, Chandler, AZ (US); Suddhasattwa Nad, Chandler, AZ (US); Jeremy Ecton, Gilbert, AZ (US); Hongxia Feng, Chandler, AZ (US); Tarek Ibrahim, Mesa, AZ (US); Brandon Marin, Chandler, AZ (US); Zhiguo Qian, Chandler, AZ (US); Sarah Blythe, Chandler, AZ (US); Bohan Shan, Chandler, AZ (US); Jason Steill, Phoenix, AZ (US); Sri Chaitra Jyotsna Chavali, Chandler, AZ (US); Leonel Arana, Phoenix, AZ (US); Dingying Xu, Chandler, AZ (US); and Marcel Wall, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,392.
Prior Publication US 2022/0102259 A1, Mar. 31, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 21/485 (2013.01); H01L 23/49827 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package substrate, comprising:
a metallization level within a dielectric material, wherein the metallization level comprises a plurality of conductive features each having a top surface and a sidewall surface,
wherein the top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness,
wherein the sidewall surface of the first conductive feature has a third average surface roughness that is greater than the second average surface roughness and the top surface of the second conductive feature has a fourth average surface roughness that is less than the first average surface roughness,
wherein the second conductive feature comprises a first material, and wherein a second material is over the top surface and the sidewall surface of the second conductive feature.