US 12,033,924 B2
Semiconductor package
Jeonghyun Lee, Seoul (KR); Hwanpil Park, Hwaseong-si (KR); and Jongbo Shim, Asan-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 6, 2021, as Appl. No. 17/542,828.
Claims priority of application No. 10-2021-0070958 (KR), filed on Jun. 1, 2021.
Prior Publication US 2022/0384320 A1, Dec. 1, 2022
Int. Cl. H01L 23/64 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/49811 (2013.01) [H01L 23/3121 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/642 (2013.01); H01L 25/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate;
an interposer;
a semiconductor chip between the package substrate and the interposer;
a plurality of conductive connectors between the package substrate and the interposer; and
a capacitor stack structure between the package substrate and the interposer, the capacitor stack structure including a first capacitor and a second capacitor stacked on the first capacitor,
wherein an upper surface of the first capacitor includes contact pads bonded to the package substrate and a lower surface of the first capacitor faces an upper surface of the second capacitor and a lower surface of the second capacitor includes contact pads bonded to the interposer, and
wherein the lower surface of the first capacitor and the upper surface of the second capacitor are insulated from each other.