US 12,033,900 B2
Trench isolation with conductive structures
Chandrashekhar Prakash Savant, Hsinchu (TW); Chia-Ming Tsai, Zhubei (TW); Yuh-Ta Fan, Shin Chu (TW); and Tien-Wei Yu, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/815,094.
Application 17/815,094 is a continuation of application No. 16/913,429, filed on Jun. 26, 2020, granted, now 11,430,700.
Prior Publication US 2023/0005796 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01)
CPC H01L 21/823842 (2013.01) [H01L 21/28088 (2013.01); H01L 21/28123 (2013.01); H01L 21/32134 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/4966 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a gate dielectric layer on a first fin structure, a second fin structure, and an insulating layer between the first and second fin structures;
forming a first work function stack on the gate dielectric layer over the first fin structure and a first portion of the insulating layer;
forming a second work function stack on the gate dielectric layer over the second fin structure and a second portion of the insulating layer, wherein the second work function stack is in contact with the first work function stack; and
forming a conductive structure between the first work function stack and the second work function stack, wherein the conductive structure is in contact with the gate dielectric layer.