US 12,033,896 B2
Isolation wall stressor structures to improve channel stress and their methods of fabrication
Aaron D. Lilak, Beaverton, OR (US); Christopher J. Jezewski, Portland, OR (US); Willy Rachmady, Beaverton, OR (US); Rishabh Mehandru, Portland, OR (US); Gilbert Dewey, Beaverton, OR (US); and Anh Phan, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 12, 2022, as Appl. No. 17/863,292.
Application 17/863,292 is a continuation of application No. 16/651,116, granted, now 11,393,722, previously published as PCT/US2018/013596, filed on Jan. 12, 2018.
Prior Publication US 2022/0352029 A1, Nov. 3, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 29/7842 (2013.01); H01L 29/7845 (2013.01); H01L 29/7846 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device structure, comprising:
a first transistor structure comprising a first gate, a first source and a first drain coupled to a first fin;
a second transistor structure adjacent to the first transistor structure, wherein the second transistor comprises a second gate, a second source and a second drain coupled to a second fin, the second fin separated from the first fin by a space;
a material comprising a metal occupying the space between the first and second fins, and adjacent to a portion of each of the first and second transistor structures, wherein the material comprising the metal is between the first and second gates, between the first source and second sources, or between the first and second drains; and
a dielectric material within the space, the dielectric material between a sidewall of the material comprising the metal and a sidewall of each of the first and second transistor structures.