US 12,033,894 B2
Gate aligned contact and method to fabricate same
Oleg Golonzka, Beaverton, OR (US); Swaminathan Sivakumar, Beaverton, OR (US); Charles H. Wallace, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 13, 2023, as Appl. No. 18/221,754.
Application 18/221,754 is a continuation of application No. 17/961,400, filed on Oct. 6, 2022, granted, now 11,756,829.
Application 17/961,400 is a continuation of application No. 17/141,157, filed on Jan. 4, 2021, granted, now 11,495,496, issued on Nov. 8, 2022.
Application 17/141,157 is a continuation of application No. 16/801,113, filed on Feb. 25, 2020, granted, now 10,910,265, issued on Feb. 2, 2021.
Application 16/801,113 is a continuation of application No. 16/412,210, filed on May 14, 2019, granted, now 10,607,884, issued on Mar. 31, 2020.
Application 16/412,210 is a continuation of application No. 15/624,036, filed on Jun. 15, 2017, granted, now 10,340,185, issued on Jul. 2, 2019.
Application 15/624,036 is a continuation of application No. 13/995,678, granted, now 9,716,037, issued on Jul. 25, 2017, previously published as PCT/US2011/066989, filed on Dec. 22, 2011.
Prior Publication US 2023/0360972 A1, Nov. 9, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 21/306 (2006.01); H01L 21/32 (2006.01); H01L 21/8234 (2006.01); H01L 23/535 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/28008 (2013.01); H01L 21/30625 (2013.01); H01L 21/76805 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/66545 (2013.01); H01L 21/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first silicon body having a longest dimension along a first direction;
a second silicon body having a longest dimension along the first direction;
a gate line over the first silicon body and over the second silicon body along a second direction, the second direction orthogonal to the first direction, wherein the gate line has an uppermost surface, and wherein the gate line comprises a high-k gate dielectric layer, and a gate electrode;
a trench contact line over the first silicon body and over the second silicon body along the second direction, the trench contact adjacent to the gate line, wherein the trench contact is continuous between the first silicon body and the second silicon body, and wherein the trench contact line has an uppermost surface at a same level as the uppermost surface of the gate line; and
a dielectric spacer laterally between the trench contact and the gate line.