US 12,033,867 B2
Method for manufacturing semiconductor device
Shunpei Yamazaki, Setagaya (JP); and Junichi Koezuka, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on May 2, 2023, as Appl. No. 18/142,213.
Application 14/043,058 is a division of application No. 13/029,148, filed on Feb. 17, 2011, granted, now 8,551,824, issued on Oct. 8, 2013.
Application 18/142,213 is a continuation of application No. 17/351,682, filed on Jun. 18, 2021, granted, now 11,682,562.
Application 17/351,682 is a continuation of application No. 16/420,854, filed on May 23, 2019, granted, now 11,049,733, issued on Jun. 29, 2021.
Application 16/420,854 is a continuation of application No. 15/492,483, filed on Apr. 20, 2017, granted, now 10,304,696, issued on May 28, 2019.
Application 15/492,483 is a continuation of application No. 14/043,058, filed on Oct. 1, 2013, granted, now 9,911,625, issued on Mar. 6, 2018.
Claims priority of application No. 2010-042024 (JP), filed on Feb. 26, 2010.
Prior Publication US 2023/0352312 A1, Nov. 2, 2023
Int. Cl. H01L 29/49 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); H01L 21/385 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/385 (2013.01) [G02F 1/134309 (2013.01); G02F 1/13439 (2013.01); G02F 1/1368 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 29/41733 (2013.01); H01L 29/4908 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); G02F 2201/123 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A liquid crystal display device comprising:
a transistor over a substrate;
a first insulating layer comprising a silicon oxide layer over the transistor;
a second insulating layer comprising a silicon nitride layer over the first insulating layer; and
a liquid crystal element over the second insulating layer,
wherein the transistor comprises:
a gate electrode over the substrate;
a gate insulating layer over the gate electrode;
an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region; and
a source electrode and a drain electrode over the oxide semiconductor layer,
wherein the liquid crystal element comprises:
a first electrode over the second insulating layer;
a second electrode over the second insulating layer;
a third insulating layer between the first electrode and the second electrode; and
a liquid crystal layer overlapping with the first electrode and the second electrode,
wherein a metal oxide region is between the source electrode or the drain electrode and the first insulating layer,
wherein one of the first electrode and the second electrode overlaps with the channel formation region, and
wherein the other of the first electrode and the second electrode does not overlap with the channel formation region.