US 12,033,858 B2
Method for fabricating a semiconductor device including a MOS transistor having a silicide layer
Young Gwang Yoon, Gyeonggi-do (KR)
Assigned to SK hynix Inc, Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 23, 2021, as Appl. No. 17/534,252.
Claims priority of application No. 10-2021-0082117 (KR), filed on Jun. 24, 2021.
Prior Publication US 2022/0415658 A1, Dec. 29, 2022
Int. Cl. H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/28097 (2013.01) [H01L 21/28088 (2013.01); H01L 21/823443 (2013.01); H01L 29/42372 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for fabricating a MOS transistor, comprising:
forming a gate dielectric material layer over a substrate;
forming a lower gate electrode material layer over the gate dielectric material layer;
performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions;
forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer;
forming an upper gate electrode material layer over the intermediate gate electrode material layer;
performing a second ion bombardment process of bombarding the upper gate electrode material layer with second ions; and
forming silicide layers in the lower gate electrode material layer and in the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.