US 12,033,711 B2
Built-in memory repair with repair code compression
Devanathan Varadarajan, Allen, TX (US); and Varun Singh, Plano, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 17, 2023, as Appl. No. 18/301,327.
Application 18/301,327 is a continuation of application No. 17/125,323, filed on Dec. 17, 2020, granted, now 11,631,472.
Prior Publication US 2023/0253062 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/16 (2006.01); G11C 29/40 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 29/16 (2013.01); G11C 29/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a first memory configured to provide a first set of defect data in a first format that specifies whether a portion of the first memory contains a defect;
a second memory configured to provide a second set of defect data in a second format that specifies whether a portion of the second memory contains a defect, wherein the second format is different from the first format; and
a controller coupled to the first memory and to the second memory and configured to:
convert each of the first set of defect data and the second set of defect data to a third format;
determine a first set of repair data for the first memory based on the first set of defect data in the third format; and
determine a second set of repair data for the second memory based on the second set of defect data in the third format.