US 12,033,704 B2
Semiconductor device
Junya Matsuno, Yokohama Kanagawa (JP); Kenro Kubota, Fujisawa Kanagawa (JP); Masato Dome, Yokohama Kanagawa (JP); Kensuke Yamamoto, Yokohama Kanagawa (JP); Kei Shiraishi, Kawasaki Kanagawa (JP); Kazuhiko Satou, Yokohama Kanagawa (JP); Ryo Fukuda, Yokohama Kanagawa (JP); and Masaru Koyanagi, Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 26, 2022, as Appl. No. 17/952,659.
Application 17/952,659 is a continuation of application No. 17/202,661, filed on Mar. 16, 2021, granted, now 11,495,308.
Claims priority of application No. 2020-157763 (JP), filed on Sep. 18, 2020.
Prior Publication US 2023/0018613 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/32 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); H10B 69/00 (2023.01)
CPC G11C 16/32 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); H10B 69/00 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage;
a second circuit coupled to the first node and configured to latch data based on a voltage of the first node; and
a third circuit coupled to the first node and configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node and output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.