| CPC G11C 16/28 (2013.01) [G11C 16/102 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] | 8 Claims |
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1. A memory device comprising:
an array of multibit memory cells, each multibit memory cell operable to store bit values for multiple physical bits in separate bit locations in a shared charge-trapping layer of a single transistor in the multibit memory cell; and
control-circuitry coupled to the array of multibit memory cells, the control-circuitry operable to:
sequentially sense a first bit value and a second bit value from one multibit memory cell based on a first current and a second current sensed from the one multibit memory cell, wherein the first current and the second current correspond to charge trapped in first bit location and second bit location respectively;
execute an algorithm on the first current and the second current, including:
sense and store the first and second current;
compare the first current to the second current to obtain a cell current; and
compare the cell current to a reference current to determine the logic state of the one multibit memory cell, wherein the cell current is a maximum cell current which is generated by applying a predetermined minimum threshold voltage to the transistor in the multibit memory cell, and wherein to compare the cell current to the reference current the maximum cell current is compared to the reference current to determine the logic state of the one multibit memory cell; and
determine based on a result of the algorithm a logic state of the one multibit memory cell.
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