US 12,033,698 B2
Method for resetting an array of resistive memory cells
Gabriel Molas, Grenoble (FR); Alessandro Bricalli, Grenoble (FR); Guiseppe Piccolboni, Verona (IT); and Amir Regev, Modiin (IL)
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR); and WEEBIT NANO LTD, Hod-Hasharon (IL)
Appl. No. 17/782,446
Filed by COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES, Paris (FR); and WEEBIT NANO LTD, Hod-Hasharon (IL)
PCT Filed Dec. 3, 2020, PCT No. PCT/EP2020/084409
§ 371(c)(1), (2) Date Jun. 3, 2022,
PCT Pub. No. WO2021/110807, PCT Pub. Date Jun. 10, 2021.
Claims priority of application No. 19306571 (EP), filed on Dec. 4, 2019.
Prior Publication US 2023/0170023 A1, Jun. 1, 2023
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0097 (2013.01) [G11C 13/004 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method for resetting an array of Resistive Memory cells, that is for putting at least one cell of the array of Resistive Memory cells in its high resistive state, by applying a sequence of N reset operations, each reset operation comprising application of a reset technique, said method comprising:
at a first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield;
at a j-th reset operation of the N−1 subsequent reset operations, j being an integer number comprised between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation;
the relative programming yield for the array of Resistive Memory cells to be reset being measured prior to the first reset operation by performing N reset operation and measuring after each reset operation the resistance of the High-Resistive State of each cell.