US 12,033,692 B2
Neural network classifier using array of three-gate non-volatile memory cells
Hieu Van Tran, San Jose, CA (US); Steven Lemke, Boulder Creek, CA (US); Vipin Tiwari, Dublin, CA (US); Nhan Do, Saratoga, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to Silicon Storage Technology, Inc., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Mar. 21, 2023, as Appl. No. 18/124,334.
Application 18/124,334 is a division of application No. 17/471,099, filed on Sep. 9, 2021, granted, now 11,646,075.
Application 17/471,099 is a division of application No. 16/382,045, filed on Apr. 11, 2019, granted, now 11,270,763, issued on Mar. 8, 2022.
Claims priority of provisional application 62/798,417, filed on Jan. 29, 2019.
Claims priority of provisional application 62/794,492, filed on Jan. 18, 2019.
Prior Publication US 2023/0223077 A1, Jul. 13, 2023
Int. Cl. G11C 11/54 (2006.01); G06N 3/045 (2023.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01)
CPC G11C 11/54 (2013.01) [G06N 3/045 (2023.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/7883 (2013.01); H10B 41/30 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A neural network device, comprising:
a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first gate disposed over and insulated from a second portion of the channel region, and a second gate disposed over and insulated from the floating gate or disposed over and insulated from the source region;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together the first gates in one of the rows of the memory cells;
a plurality of second lines each electrically connecting together the second gates in one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of fourth lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive the first plurality of inputs as electrical voltages on the plurality of second lines or on the plurality of fourth lines, and to provide the first plurality of outputs as electrical currents on the plurality of third lines.