US 12,033,690 B2
Sense amplifier, memory and control method
Hsin-Cheng Su, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 16, 2022, as Appl. No. 17/842,161.
Application 17/842,161 is a continuation of application No. PCT/CN2021/107681, filed on Jul. 21, 2021.
Claims priority of application No. 202110314347.3 (CN), filed on Mar. 24, 2021.
Prior Publication US 2022/0319579 A1, Oct. 6, 2022
Int. Cl. G11C 7/12 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A sense amplifier (SA), comprising:
an amplifying module, configured to amplify voltage difference between a Bit Line (BL) and a Bit Line Benchmark (BLB) when the SA is in an amplifying stage;
a controllable power module, connected to the amplifying module and configured to stop providing power to the amplifying module when the SA is in a writing stage, to enable the amplifying module to stop working; and
a writing module, connected to the BL and the BLB, and configured to pull the voltage difference between the BL and the BLB according to data to be written when the SA is in the writing stage;
wherein the controllable power module is configured to:
provide power to the amplifying module when the SA is in a recovery stage, to enable the amplifying module to continue to work.