| CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0295 (2013.01)] | 18 Claims |
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1. A gate driver comprising a plurality of stages, wherein each of the stages includes:
a first output part configured to output a carry signal in response to a voltage of a first node;
a first input part configured to control the voltage of the first node in response to a previous carry signal;
a second input part configured to control the voltage of the first node in response to a first next carry signal;
a second output part configured to output a scan signal in response to the voltage of the first node;
a third output part configured to output a sensing signal in response to the voltage of the first node; and
a scan signal control part configured to apply a first low power voltage to an output terminal of the second output part to which the scan signal is output in response to a second next carry signal of which a pulse is generated before a pulse of the first next carry signal,
wherein the first output part includes:
a 2-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a carry clock signal, and a second electrode connected to an output terminal of the first output part; and
a 2-2th transistor including a control electrode connected to a second node, a first electrode configured to receive a second low power voltage, and a second electrode connected to the output terminal of the first output part,
wherein the second output part includes:
a 3-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a scan clock signal, and a second electrode connected to the output terminal of the second output part; and
a 3-2th transistor including a control electrode connected to the second node, a first electrode configured to receive the first low power voltage, and a second electrode connected to the output terminal of the second output part, and
wherein the third output part includes:
a 4-1th transistor including a control electrode connected to the first node, a first electrode configured to receive a sensing clock signal, and a second electrode connected to an output terminal of the third output part; and
a 4-2th transistor including a control electrode connected to the second node, a first electrode configured to receive the first low power voltage, and a second electrode connected to the output terminal of the third output part,
wherein the output terminal of the first output part is directly connected to only-the 2-1th transistor and the 2-2th transistor, and
wherein the output terminal of the third output part is directly connected to only the 4-1th transistor and the 4-2th transistor.
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