US 12,033,239 B2
Dead surface invalidation
Priyadarshi Sharma, Santa Clara, CA (US); Anshuman Mittal, Santa Clara, CA (US); and Saurabh Sharma, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 28, 2021, as Appl. No. 17/563,950.
Prior Publication US 2023/0206384 A1, Jun. 29, 2023
Int. Cl. G06T 1/20 (2006.01); G06F 12/0891 (2016.01); G06T 1/60 (2006.01)
CPC G06T 1/60 (2013.01) [G06F 12/0891 (2013.01); G06T 1/20 (2013.01); G06F 2212/455 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising a command processor comprising circuitry configured to:
maintain mappings of draw call identifiers (IDs) to dead surface IDs;
receive a discard surface notification corresponding to an end of draw pipe notification for a first draw call; and
responsive to a determination that any surfaces associated with the discard surface notification should be invalidated, convey a cache invalidation signal identifying a first surface to a cache, responsive to the first surface being associated with the discard surface notification.