US 12,033,237 B2
Dynamic precision management for integer deep learning primitives
Naveen K. Mellempudi, Bangalore (IN); Dheevatsa Mudigere, Bangalore (IN); Dipankar Das, Pune (IN); and Srinivas Sridharan, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 24, 2023, as Appl. No. 18/306,033.
Application 16/853,405 is a division of application No. 15/881,991, filed on Jan. 29, 2018, granted, now 10,643,297, issued on May 5, 2020.
Application 18/306,033 is a continuation of application No. 17/730,364, filed on Apr. 27, 2022, granted, now 11,669,933.
Application 17/730,364 is a continuation of application No. 17/083,588, filed on Oct. 29, 2020, granted, now 11,321,805, issued on May 3, 2022.
Application 17/083,588 is a continuation of application No. 16/853,405, filed on Apr. 20, 2020, granted, now 10,825,127, issued on Nov. 3, 2020.
Claims priority of provisional application 62/501,796, filed on May 5, 2017.
Prior Publication US 2023/0351542 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 1/20 (2006.01); G06F 5/01 (2006.01); G06F 7/501 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06F 17/15 (2006.01); G06F 17/16 (2006.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G06N 3/084 (2023.01)
CPC G06T 1/20 (2013.01) [G06F 5/01 (2013.01); G06F 7/501 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 17/153 (2013.01); G06F 17/16 (2013.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06N 3/084 (2013.01); G06F 2207/382 (2013.01); G06F 2207/4824 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processing unit comprising:
an interface coupled to an interconnect fabric; and
a graphics core cluster including a plurality of multiprocessors that are interconnected via a data interconnect, a multiprocessor of the plurality of multiprocessors including circuitry configured to:
convert elements of a floating-point tensor into elements of a fixed-point tensor, wherein to convert an element of the floating-point tensor, the circuitry is to compute a right-shift value based on a run-time configurable scale factor associated with the floating-point tensor and right-shift a mantissa of the element based on the right-shift value to generate a magnitude integer;
perform a compute operation on input including data elements of the fixed-point tensor; and
generate an output tensor via the compute operation.