US 12,032,972 B2
Methods, apparatus, and articles of manufacture to improve performance of a compute device by detecting a scene change
Anatoly Litvinov, Binyamina (IL); Ilya Sister, Haifa (IL); Andrey Semenjatshenco, Giv'atayim (IL); and Nir Gerber, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 31, 2022, as Appl. No. 17/829,315.
Prior Publication US 2022/0291930 A1, Sep. 15, 2022
Int. Cl. G06F 1/24 (2006.01); G06F 1/3296 (2019.01); G06F 9/00 (2018.01); G06F 9/445 (2018.01); G06F 11/34 (2006.01); G06V 10/62 (2022.01); G06V 10/74 (2022.01); G06V 10/75 (2022.01)
CPC G06F 9/44505 (2013.01) [G06F 1/3296 (2013.01); G06F 11/3409 (2013.01); G06V 10/62 (2022.01); G06V 10/761 (2022.01); G06V 10/758 (2022.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus to improve performance of a compute device by detecting a scene change, the apparatus comprising:
interface circuitry to collect data from an image sensor; and
first processor circuitry including one or more of:
at least one of a central processor unit (CPU), a graphics processor unit (GPU), a digital signal processor (DSP), or a microcontroller unit (MCU), the at least one of the CPU, the GPU, the DSP, or the MCU having control circuitry to control data movement within the first processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions including neural network instructions, and one or more registers to store a first result of the one or more first operations, the instructions in the apparatus;
a Field Programmable Gate Array (FPGA), the FPGA including first logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the first logic gate circuitry and the plurality of the configurable interconnections to perform one or more second operations, the storage circuitry to store a second result of the one or more second operations; or
Application Specific Integrated Circuitry (ASIC) including second logic gate circuitry to perform one or more third operations;
the first processor circuitry to perform at least one of the first operations, the second operations, or the third operations to instantiate:
scene change detection circuitry to:
determine a first score value for a first metric of similarity between a first image of a field of view (FOV) of the image sensor and a second image of the FOV;
determine a second score value for a second metric of similarity between the first image and the second image; and
compute a composite score value based on the first score value and the second score value; and
interrupt circuitry to, based on the composite score, generate an interrupt to second processor circuitry of the compute device to cause the second processor circuitry to adjust power consumption of the compute device by at least one of (a) transitioning between a sleep mode of operation and a wake mode of operation or (b) adjusting a complexity of image processing to be performed by the second processor circuitry.