US 12,032,892 B2
Semiconductor layout context around a point of interest
David A. Abercrombie, Apex, NC (US); Mohamed Alimam Mohamed Selim, Tokyo (JP); Mohamed Bahnas, Cupertino, CA (US); Hazem Hegazy, Cairo (EG); and Ahmed Hamed Fathi Hamed, Giza (EG)
Assigned to Siemens Industry Software Inc., Plano, TX (US)
Appl. No. 17/638,315
Filed by Siemens Industry Software Inc., Plano, TX (US)
PCT Filed Aug. 30, 2019, PCT No. PCT/US2019/049066
§ 371(c)(1), (2) Date Feb. 25, 2022,
PCT Pub. No. WO2021/040733, PCT Pub. Date Mar. 4, 2021.
Prior Publication US 2022/0309222 A1, Sep. 29, 2022
Int. Cl. G06F 30/392 (2020.01); G06F 30/27 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/27 (2020.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for analyzing a plurality of points of interest (POIs) in a semiconductor layout design for a downstream application, the method comprising:
accessing one or more kernels based on the downstream application, the one or more kernels when convolved with a representation of the semiconductor layout design extracting at least one feature associated with the plurality of POIs, the extracted at least one feature for use by the downstream application;
for a respective POI of the plurality of POIs, convolving the one or more kernels with the representation of the semiconductor layout design in order to generate a signature for the respective POI, wherein the one or more kernels comprise a set of mutually exclusive rings centered about the respective POI in order to generate the signature, the signature comprising a numerical representation indicative of the extracted at least one feature associated with the respective POI; and
analyzing, based on the downstream application, the signature for the extracted at least one feature associated with the respective POI.