US 12,032,887 B2
In-graph causality ranking for faults in the design of integrated circuits
Xiang Gao, San Jose, CA (US); Hsiang-Chieh Liao, San Ramon, CA (US); Chia-Chih Yen, Taipei (TW); and Sashikala Venkata Obilisetty, Los Altos, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 10, 2022, as Appl. No. 17/669,307.
Claims priority of provisional application 63/149,965, filed on Feb. 16, 2021.
Prior Publication US 2022/0261524 A1, Aug. 18, 2022
Int. Cl. G06F 30/33 (2020.01); G06F 30/31 (2020.01); G06F 30/3312 (2020.01); G06F 30/3323 (2020.01); G06F 30/398 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 30/31 (2020.01); G06F 30/3312 (2020.01); G06F 30/3323 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to perform a method comprising:
accessing a graph that represents signal flow through a design of an integrated circuit, the graph comprising a plurality of graph elements;
constructing a first propagation model for propagation of faults through the graph, the first propagation model comprising local propagation models for propagation of faults through the graph elements;
modeling propagation of a known fault backward through the graph using the first propagation model to develop a causality ranking of the graph elements as possible causes of the known fault; and
based on the modeled fault propagation, causing display of information indicative of the causality ranking in a user interface that shows the design of the integrated circuit.