US 12,032,853 B2
Data relocation scheme selection for a memory system
Rakeshkumar Dayabhai Vaghasiya, Hyderabad (IN); Nicola Colella, Capodrise (IT); Mani Raghavendra Aravapalli, Hyderabad (IN); Anil Sindhi, Hyderabad (IN); and Dhruv Chauhan, Hyderabad (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 25, 2022, as Appl. No. 17/584,077.
Prior Publication US 2023/0236762 A1, Jul. 27, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0647 (2013.01); G06F 3/0679 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
determine to relocate data associated with a logical block associated with the one or more memory devices;
select, after determining to relocate the data associated with the logical block and based at least in part on a fragmentation characteristic of the data associated with the logical block, whether to perform either a relocation operation associated with relocating invalid data of the logical block or a relocation operation associated with refraining from relocating invalid data of the logical block; and
perform the selected relocation operation on the logical block based at least in part on determining to relocate the data associated with the logical block.