US 12,032,845 B2
Memory controller partitioning for hybrid memory system
Frederick A. Ware, Los Altos, CA (US); and John Eric Linstadt, Palo Alto, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Oct. 19, 2021, as Appl. No. 17/505,503.
Application 17/505,503 is a continuation of application No. PCT/US2020/028003, filed on Apr. 13, 2020.
Claims priority of provisional application 62/839,456, filed on Apr. 26, 2019.
Prior Publication US 2022/0066672 A1, Mar. 3, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0644 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory module comprising:
at least one slow memory component defining a large address space, the large address space to store data at slow-memory-component addresses;
at least one fast memory component defining a small address space, the small address space to cache the data stored in the large address space;
a hybrid controller component linked to the slow memory component and the fast memory component, the hybrid controller component to issue a request for at least one access time slot, receive an access-time-slot command identifying a requested access time slot responsive to the request for at least one access time slot, and, responsive to the access-time-slot command, copy a cache line in the requested access time slot from the slow memory component to the fast memory component; and
a command interface to pass the request for at least one access time slot and the access-time-slot command;
wherein the access-time-slot command is a first access-time-slot command directed to a first bank of the fast memory and is received in a command format that includes a second access-time-slot command directed to a second bank of the fast memory.