US 12,032,840 B2
System level hardware mechanisms for dynamic assist control
Anand Shanmugam Sundararajan, Chennai (IN); Narayan Kulshrestha, Fremont, CA (US); Ka Yun Lee, Cupertino, CA (US); Brian Smith, Mountain View, CA (US); Madhukiran V. Swarna, Portland, OR (US); Ramachandiran V, Bangalore (IN); and Kevin Wilder, Wilmette, IL (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Feb. 23, 2022, as Appl. No. 17/678,784.
Prior Publication US 2023/0266899 A1, Aug. 24, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0634 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for controlling a memory device performance feature, the method comprising:
selecting a first threshold voltage from among a temperature variable threshold voltage and a fixed threshold voltage;
determining that an operating voltage received from a voltage regulator external to a memory device has crossed the first threshold voltage in a first direction;
in response, enabling the memory device performance feature for a first memory device;
determining that the operating voltage has crossed a second threshold voltage in a second direction; and
in response, disabling the memory device performance feature for the first memory device.