US 12,032,839 B2
Hierarchical power management of memory for artificial reality systems
Shrirang Madhav Yardi, San Jose, CA (US); Gregory Edward Ehmann, Sleepy Hollow, IL (US); Ennio Salemi, Palo Alto, CA (US); George Spatz, Lake Zurich, IL (US); and Jeffrey Ryden, Kirkland, WA (US)
Assigned to Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed by Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed on Jul. 31, 2020, as Appl. No. 16/947,432.
Claims priority of provisional application 63/047,035, filed on Jul. 1, 2020.
Prior Publication US 2022/0004328 A1, Jan. 6, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 1/28 (2006.01); G06T 19/00 (2011.01); G06F 3/01 (2006.01)
CPC G06F 3/0634 (2013.01) [G06F 1/28 (2013.01); G06F 3/0625 (2013.01); G06F 3/064 (2013.01); G06F 3/0673 (2013.01); G06T 19/006 (2013.01); G06F 3/011 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An artificial reality system comprising:
a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content for display, the device comprising:
a memory divided into a plurality of memory blocks, each memory block configured to operate in a plurality of power modes independently of each other memory block;
a memory decoder connected to each of the memory blocks, wherein the memory decoder:
receives a request to access a memory address;
determines a memory block included in the plurality of memory blocks to which the memory address corresponds; and
provides an enable signal for an event input of the memory block due at least in part to the memory address corresponding to the memory block;
a memory block controller connected to the memory block and the memory decoder, wherein the memory block controller:
includes a control register that defines a state machine that controls a power state of the memory block; and
receives the enable signal for the event input of the memory block, the enable signal causing the power state of the memory block to transition based at least in part on the state machine; and
a memory power controller connected to the memory block controller, wherein the memory power controller configures the state machine via the control register such that, when the memory block controller receives the enable signal, the power state of the memory block controller transitions from a lower power mode included in the plurality of power modes to a higher power mode included in the plurality of power modes to facilitate accessing the memory address in connection with the request, wherein:
the memory decoder stops providing the enable signal for the event input of the memory block; and
the memory block controller causes the power state of the memory block to return from the higher power mode to the lower power mode due at least in part to the memory decoder having stopped providing the enable signal for the event input of the memory block.