US 12,032,833 B2
Management of error-handling flows in memory devices using probability data structure
Aswin Thiruvengadam, Folsom, CA (US); and Vamsi Pavan Rayaprolu, Santa Clara, CA (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 12, 2022, as Appl. No. 17/943,082.
Prior Publication US 2024/0086075 A1, Mar. 14, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload;
obtaining error recovery data as a result of running the sample data; and
determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.