US 12,032,829 B2
Memory device performing in-memory operation and method thereof
Seon Wook Kim, Namyangju-si (KR); Yoonah Paik, Seoul (KR); Changhyun Kim, Seongnam-si (KR); and Won Jun Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 11, 2022, as Appl. No. 17/861,569.
Claims priority of application No. 10-2021-0095294 (KR), filed on Jul. 21, 2021; and application No. 10-2022-0018015 (KR), filed on Feb. 11, 2022.
Prior Publication US 2023/0028952 A1, Jan. 26, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory banks each configured to perform an operation based on first operand data including pieces of first unit data and second operand data including pieces of second unit data; and
a processing in-memory interface unit (PIM IU) configured to deliver signals for an operation request to the plurality of memory banks,
wherein each of the plurality of memory banks includes,
a memory cell array configured to store one of the pieces of first unit data, and
a PIM engine configured to,
read the one of the pieces of first unit data from the memory cell array,
receive the pieces of second unit data broadcast from any one memory bank among to the plurality of memory banks to the remaining memory banks, and
generate an operation result by performing an operation based on the one of the pieces of first unit data and the pieces of second unit data, and
wherein the PIM engine configured to perform the operation based on the one of the pieces of first unit data and the pieces of second unit data, after all of the pieces of first unit data are read from all of the plurality of memory banks and the pieces of second unit data are received.