US 12,032,827 B2
Memory devices and systems for host controlled enablement of automatic background operations in a memory device
Francesco Falanga, Pozzuoli (IT); and Danilo Caraccio, Buonalbergo (IT)
Assigned to Lodestar Licensing Group LLC, Evanston, IL (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Mar. 11, 2022, as Appl. No. 17/692,241.
Application 16/361,445 is a division of application No. 15/131,447, filed on Apr. 18, 2016, granted, now 10,282,102, issued on May 7, 2019.
Application 15/131,447 is a division of application No. 13/739,453, filed on Jan. 11, 2013, granted, now 9,329,990, issued on May 3, 2016.
Application 17/692,241 is a continuation of application No. 16/361,445, filed on Mar. 22, 2019, granted, now 11,275,508.
Prior Publication US 2022/0197504 A1, Jun. 23, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0665 (2013.01); G06F 3/0689 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7211 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an array of memory cells;
a first register;
a second register storing a first value of the second register;
a controller for access of the array of memory cells, the controller configured to:
autonomously perform background operations on the array of memory cells in response to the first register storing a first value of the first register;
prohibit autonomous performance of the background operations on the array of memory cells in response to the first register storing a second value of the first register different than the first value of the first register;
write a second value of the second register, different than the first value of the second register, to the second register in response to control signals received by the memory device and indicative of a desire to write the second value of the second register to the second register; and
initiate performance of the background operations on the array of memory cells in response to the second register storing the second value of the second register.