US 12,032,766 B2
Apparatus and method for driving display
Jong Min Park, Daejeon (KR); Seong Sik Yoon, Daejeon (KR); and Jung Min Choi, Daejeon (KR)
Assigned to Silicon Works Co., Ltd., Daejeon (KR)
Filed by SILICON WORKS CO., LTD., Daejeon (KR)
Filed on Mar. 2, 2023, as Appl. No. 18/177,296.
Application 18/177,296 is a continuation of application No. 17/367,811, filed on Jul. 6, 2021, granted, now 11,620,011.
Claims priority of application No. 10-2020-0084693 (KR), filed on Jul. 9, 2020.
Prior Publication US 2023/0205346 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/041 (2006.01); G09G 3/20 (2006.01); G09G 5/00 (2006.01)
CPC G06F 3/0412 (2013.01) [G06F 3/04184 (2019.05); G09G 3/20 (2013.01); G09G 5/008 (2013.01); G09G 2330/021 (2013.01); G09G 2340/0435 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A display driving device comprising:
a source driver IC (integrated circuit) configured to operate in a first low power mode in which an analog data processing circuit is deactivated, or operate in a second low power mode in which both of the analog data processing circuit and a digital data processing circuit are deactivated, during a touch sensing period of a first frame;
a readout IC configured to supply touch sensor driving signals to touch sensors during the touch sensing period, and receive touch sensing data from the touch sensors according to the touch sensor driving signals; and
a timing controller configured to generate, during a display period of the first frame, a clock embedded data signaling (CEDS) packet including clock training data, control data, and image data, and transmit the CEDS packet to the source driver IC,
wherein, when the source driver IC operates in the first low power mode or the second low power mode during the touch sensing period, the timing controller sets a first voltage (VCEDN) and a second voltage (VCEDP) for generating the clock training data to the same level, control the source driver IC to be a high-impedance (Hi-Z) state or control the clock training data to be maintained at a predetermined level to prevent the clock training data from being transmitted.