| CPC G06F 15/17312 (2013.01) [G06F 15/17 (2013.01); G06F 15/17337 (2013.01); H04L 12/44 (2013.01); G06N 3/063 (2013.01); H04L 43/0864 (2013.01)] | 14 Claims |
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1. An inter-chip timing synchronization method comprising:
for each pair of integrated circuit chips in a plurality of chips of a semiconductor device,
determining a first one-way latency for transmissions from a first integrated circuit chip in the pair to a second integrated circuit chip in the pair of integrated circuit chips, and
determining a second one-way latency for transmissions from the second integrated circuit chip in the pair to the first integrated circuit chip in the pair of integrated circuit chips;
receiving, at a semiconductor device driver, the first one-way latency and the second one-way latency for each pair of integrated circuit chips;
determining, by the semiconductor device driver and from the respective first one-way latency and the second one-way latency for each pair of integrated circuit chips, a loop latency between each pair of integrated circuit chips; and
adjusting, by the semiconductor device driver and for at least one pair of integrated circuit chips, a local counter of the second integrated circuit chip in the at least one pair of integrated circuit chips based on a characteristic inter-chip latency of the semiconductor device and the first one-way latency of the at least one pair of integrated circuit chips.
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