CPC G06F 13/4243 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3237 (2013.01); G06F 1/3275 (2013.01); Y02B 70/10 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08)] | 20 Claims |
1. A controller, comprising:
an interface to transmit, to at least a first memory device and a second memory device, a first command that indicates a read of a status register;
a first receiver circuit to serially receive information from the status register; and
a second receiver to receive a resume signal collectively from the first memory device and the second memory device that indicates whether the first memory device and the second memory device are collectively ready to receive a clock signal that synchronizes a transmission of the information from the status register.
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