US 12,032,487 B2
Access log and address translation log for a processor
Benjamin T. Sander, Austin, TX (US); Mark Fowler, Boxborough, MA (US); Anthony Asaro, Markham (CA); Gongxian Jeffrey Cheng, Markham (CA); and Michael Mantor, Orlando, FL (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Feb. 8, 2022, as Appl. No. 17/666,974.
Application 17/666,974 is a continuation of application No. 14/747,980, filed on Jun. 23, 2015, granted, now 11,288,205.
Prior Publication US 2022/0269620 A1, Aug. 25, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/10 (2016.01); G06F 12/0893 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/1027 (2013.01) [G06F 12/0893 (2013.01); G06F 2212/684 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
recording, at a processor, a first log indicating a set of physical memory addresses associated with a stream of cache misses at the processor;
providing the first log to an operating system executing at the processor; and
transferring data to a first cache based on the first log.