CPC G06F 12/1027 (2013.01) [G06F 11/073 (2013.01); G06F 2212/657 (2013.01); G06F 2212/683 (2013.01)] | 51 Claims |
1. A processor comprising:
a decode circuit to decode a memory access instruction, the memory access instruction to indicate one or more memory address operands, the one or more memory address operands to have address generation information and metadata; and
an execution circuit coupled with the decode circuit, the execution circuit to:
generate a 64-bit virtual address based on the one or more memory address operands, the 64-bit virtual address having a bit 63 to indicate whether the 64-bit virtual address corresponds to user level or supervisor level, an X-bit address field starting at a bit 0 to store an address generated from the address generation information, and one or more metadata bits to store the metadata; and
perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits.
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