US 12,032,485 B2
64-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s)
Vedvyas Shanbhogue, Austin, TX (US); Gilbert Neiger, Portland, OR (US); Stephen Robinson, Austin, TX (US); Dan Baum, Haifa (IL); and Ron Gabor, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/133,570.
Prior Publication US 2022/0197822 A1, Jun. 23, 2022
Int. Cl. G06F 12/10 (2016.01); G06F 11/07 (2006.01); G06F 12/1027 (2016.01)
CPC G06F 12/1027 (2013.01) [G06F 11/073 (2013.01); G06F 2212/657 (2013.01); G06F 2212/683 (2013.01)] 51 Claims
OG exemplary drawing
 
1. A processor comprising:
a decode circuit to decode a memory access instruction, the memory access instruction to indicate one or more memory address operands, the one or more memory address operands to have address generation information and metadata; and
an execution circuit coupled with the decode circuit, the execution circuit to:
generate a 64-bit virtual address based on the one or more memory address operands, the 64-bit virtual address having a bit 63 to indicate whether the 64-bit virtual address corresponds to user level or supervisor level, an X-bit address field starting at a bit 0 to store an address generated from the address generation information, and one or more metadata bits to store the metadata; and
perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits.