US 12,032,441 B2
Systems and methods for an ECC architecture with memory mapping
Xiaoming Zhu, San Jose, CA (US); Jie Chen, Milpitas, CA (US); Bo Fu, Cupertino, CA (US); and Zining Wu, Los Altos, CA (US)
Assigned to InnoGrit Technologies Co., Ltd., Shanghai (CN)
Filed by InnoGrit Technologies Co., Ltd., Shanghai (CN)
Filed on Jun. 30, 2023, as Appl. No. 18/216,628.
Application 18/216,628 is a continuation of application No. 17/555,635, filed on Dec. 20, 2021, granted, now 11,734,109.
Application 17/555,635 is a continuation of application No. 16/354,231, filed on Mar. 15, 2019, granted, now 11,237,902, issued on Feb. 1, 2022.
Prior Publication US 2023/0342248 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/30 (2006.01); G06F 12/02 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/3034 (2013.01); G06F 12/0246 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A storage controller, comprising:
a first interface configured to receive data from and transmit data to a host computing system;
a multi-channel interface configured to transfer encoded data over a plurality of channels in parallel, with one or more non-volatile storage devices;
an error correction code (ECC) processor configured to encode the data and decode the encoded data;
wherein the ECC processor comprises a memory comprising a plurality of memory units configured to provide temporary storage for the encoded data;
wherein the ECC processor comprises a mapping storage configured to store a plurality of memory mapping entries each indicating whether a memory unit is allocated to a channel;
wherein the ECC processor further comprises:
an ECC engine that has at least one ECC encoder and at least one ECC decoder;
an encoding task control; and
a decoding task control, wherein the encoding task control is configured to control write task(s) and provide a first set of one or more memory units of the plurality of memory units to the at least one encoder and the multi-channel interface to accomplish the write task(s), and the decoding task control is configured to control read task(s) and provide a second set of one or more memory units of the plurality of memory units to the at least one decoder and the multi-channel interface to accomplish the read task(s);
a quality of service (QoS) monitor configured to determine a memory mapping update based on one or more criteria selected from a group including: a total number of pending read tasks, a total number of pending write tasks, next expected task from a non-volatile storage device, pending retry tasks, idle channel, 4K random read, traffic congestion, and sequential write.