US 12,032,439 B2
Memory including error correction circuit and operation method of memory
Gang Sik Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 1, 2023, as Appl. No. 18/104,713.
Claims priority of application No. 10-2022-0140094 (KR), filed on Oct. 27, 2022.
Prior Publication US 2024/0143438 A1, May 2, 2024
Int. Cl. G06F 11/10 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/1044 (2013.01) [G11C 29/52 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory comprising:
a memory core including a plurality of memory regions;
a refresh-excluded region storing circuit suitable for storing therein information on a refresh-excluded region where no valid data is stored, on which a refresh operation is not to be performed among the memory regions;
an error correction circuit suitable for correcting an error in data read from the memory core based on an error correction code read from the memory core;
an error check operation control circuit suitable for performing an error check operation of checking an error in the read data by using the error correction circuit;
a bad region classifying circuit suitable for classifying a selected memory region as a bad region based on an error, which is detected in data read from the selected memory region during the error check operation; and
a blocking circuit suitable for preventing the bad region classifying circuit from classifying the refresh-excluded region as a bad region based on the information stored in the refresh-excluded region storing circuit.