US 12,032,349 B2
Controller
Hidehiko Sekimoto, Kyoto (JP)
Assigned to OMRON CORPORATION, Kyoto (JP)
Appl. No. 17/614,722
Filed by OMRON Corporation, Kyoto (JP)
PCT Filed Feb. 21, 2020, PCT No. PCT/JP2020/007162
§ 371(c)(1), (2) Date Nov. 29, 2021,
PCT Pub. No. WO2020/255486, PCT Pub. Date Dec. 24, 2020.
Claims priority of application No. 2019-114346 (JP), filed on Jun. 20, 2019.
Prior Publication US 2022/0221833 A1, Jul. 14, 2022
Int. Cl. G05B 19/05 (2006.01)
CPC G05B 19/056 (2013.01) [G05B 19/058 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A control device including a first program in a first execution format in which an entirety of the first program is executed per a predetermined control cycle, and a second program in a second execution format in which parts of the second program are sequentially executed by an interpreter, the device comprising:
a first processor configured to execute the first program in the first execution format per the predetermined control cycle (i) to calculate a first command value for controlling a first control target and (ii) to control a second control target;
a second processor configured to execute the second program in the second execution format to calculate a second command value for controlling the second control target per the predetermined control cycle in accordance with an intermediate code generated by the interpreter interpreting at least a part of the second program in the second execution format, and to calculate the second command value for controlling the second control target in response to the first processor executing the first program in the first execution format; and
an interface configured to output the first command value and the second command value per the predetermined control cycle,
wherein the second processor is configured to permit, in response to an overlap between a time to execute the first program in the first execution format and a time to execute the second program in the second execution format for controlling the second control target, execution of one of the first program or the second program that issued an occupation request to the second processor earlier than the other one of the first program or the second program per the predetermined control cycle.