CPC G04F 10/005 (2013.01) [H03L 7/08 (2013.01)] | 20 Claims |
1. A Time to Digital Converter, TDC, arrangement comprising:
a first delay circuit configured to:
receive a signal with multiple phases; and
output a delayed signal with corresponding multiple phases;
a set of phase detectors configured to:
compare each phase of the multiple phases of the signal with a reference signal;
a first multiplexer configured to:
receive the delayed signal; and
output a selected one of the phases of the delayed signal in response to outputs from the set of phase detectors;
a second delay circuit configured to:
receive the reference signal; and
output a delayed reference signal; and
a TDC configured to:
detect a time difference between the delayed reference signal and the selected one of the phases of the delayed signal.
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